Research

FPGA-Based Design of High-Speed 50G-PON LDPC Encoder And Decoder

  • 50Gbps seamless encoding and decoding throughput on an FPGA board.
  • Our design meets 50G-PON standard.
    • - COLLABORATED WITH ETRI AND CAU

    ZeBRA: Precisely Destroying Neural Networks with Zero-Data Based Repeated Bit Flip Attack

  • Zero-data based repeated bit flip attack that precisely destroys deep neural networks (DNNs) by synthesizing its own attack datasets.
  • Our experimental results show that 2.0x (CIFAR-10) and 1.6x (ImageNet) less number of bit flips are required on average to destroy DNNs compared to the previous attack method.
  • Our code is available at github .
    • - Collaborated with DGIST

    Minimal Aliasing Error Correction Codes for DDR5 Reliability Improvement

  • Minimal aliasing code among a class of systematic single-error-correction codes that are suitable to be implemented within DDR5 DRAM die.
    • - Collaborated with Intel Corporation and Sungkyunkwan University

    Latency-optimized Design of Data Bus Inversion

  • Encoders for data bus inversion (DBI), which conventionally uses a majority voter to pick a data representation that minimizes switching activities and thus reduces the corresponding energy consumption.
  • The new encoders employ simpler approximate voters comprising only two gate levels, which improve latency more than twice while still achieving switching activity savings by 9% and 11%, respectively.

    • Area Optimization Techniques for High-Density Spin-Orbit Torque MRAMs

  • Area optimization techniques for high-density spin-orbit torque magnetic random-access memories.
  • Proposed techniques can achieve a bit-cell area reduction of 10–25% compared to the conventional SOT-MRAM. The comparison of our proposed designs with the standard spin-transfer torque MRAM shows 45% lower write energy, 84% lower read energy, and 2.3x higher read-disturb margin.

    • Credit Card Number Recognition for People with Visual Impairment

  • The conventional credit card number recognition system generally needs a card to be placed in a designated location before its processing, which is not an ideal user experience especially for people with visual impairment.
  • To improve the user experience, this research proposes a novel algorithm that can automatically detect the location of a credit card number based on the fact that a group of sixteen digits has a fixed aspect ratio.